1. Field of the Invention
The present invention relates to a semiconductor device and a method for manufacturing the same. In particular, it relates to a semiconductor device provided with a local interconnection for making electrical connection among conductive regions and a method of manufacturing the same.
2. Description of the Prior Art
In order to increase the packing density of semiconductor devices, the areas of the constituent components and the necessary interconnections for interconnection thereamong have to be reduced and compacted. A variety of approaches have been proposed to this end.
The multilayer interconnection employed in the field is manufactured by alternately forming interconnections and insulating films. Namely, after formation of a first interconnection, an insulating film is formed over the first interconnection followed by forming a second interconnection on the insulating film.
The upper second interconnection and the lower first interconnection are connected to each other via a contact hole opened through the interlayer insulating film. However, when forming contact holes, an adequate margin for aligning masks has to be provided and, it becomes difficult by the necessity for the margin to miniaturize semiconductor devices.
Recently, in such a situation, those skilled in the art have taken an increasing interest in the possibilities of local interconnection, by which a interconnection can be connected to a near impurity diffusion region by means of a conductive film without making use of an interlayer insulating film and contact holes opened therethrough.
The local interconnection is formed by forming and patterning a metallic film over an electrode formed on a semiconductor substrate and an impurity diffusion region formed within the semiconductor substrate.
Examples of this technique are described in U.S. Pat. No. 4,746,219. In these cases, an electrode and an impurity diffusion region are connected by local interconnection after forming a salicide film (self-aligned silicide film) on the electrode and the impurity diffusion region for the purpose of decreasing the contact resistance of the interconnection.
Next, the method for manufacturing the local interconnection will be briefly explained in accordance with the Patent.
In FIG. 1A, an impurity diffusion region 103 is formed within a semiconductor substrate 101 surrounded by a field oxide film 102. Also, a first interconnection 104 of polysilicon is formed on the field oxide film 102 and provided with a sidewall oxide film 105 on the flank of the first interconnection 104. The conductivity type of the impurity diffusion region 103 is p-type when the conductivity type of the semiconductor substrate 101 is n-type.
In this situation, after forming a titanium (Ti) film 106, the first interconnection 104 and the impurity diffusion region 103 are heated together with titanium film 106 to form a titanium silicide film 107 by a reaction between titanium and silicon of the upper surfaces of the first interconnection 104 and the impurity diffusion region 103 as illustrated in FIG. 1B.
The titanium film 106 is then removed by etching, leaving the titanium silicide film 107 on the first interconnection 104 and the impurity diffusion region 103.
Next, as illustrated in FIGS. 1C and 1D, a titanium nitride film 108 is formed over the entire surface of the structure followed by patterning the titanium nitride film 108 to form a local interconnection 109.
The etching of the titanium nitride film 108 is carried out with a mixed gas composed of CF.sub.4 and Cl.sub.2. In the case of the etching with the mixed etchant gas, the semiconductor substrate 101 comes to slightly appear through the very thin edge of the field oxide film 102 which is removed from the semiconductor substrate 101 during the over-etching of the titanium nitride film 108, even though the field oxide film 102 is etched only very slightly by the etchant gas. As a result, the semiconductor substrate 101 is etched along the periphery of the field oxide film 102 by the etchant gas for titanium nitride to form a groove 110.
In this condition, when another interconnection is formed at the level upper than the local interconnection 109 over the groove 110, it may be the case that leakage current is passed across the PN junction between the impurity diffusion region 103 and the semiconductor substrate 101.
Furthermore, grooves such as the groove 110 can be formed also at the periphery of the first interconnection 104. This is because the upper portion of the sidewall oxide film 105 is etched, and therefore polysilicon of the first interconnection 104 is etched.
The interconnection resistance is varied when the shape of the first interconnection 104 is deformed. Also, when the first interconnection 104 serves as the gate electrode of a MOS transistor, the threshold voltage may be varied beyond the tolerance thereof, resulting in a problem of unstable operation of the transistor.
These problems are the cases also when the titanium silicide film 107 is not formed.